CDRs are well known and widely used in the electronics industry. Within the digital field, CDR are used in a variety of applications. Such applications include, for example, wireline communications such as PCI express and SATA, and optical communications such as SONET and GPON. CDRs are typically designed to perform within a given set of boundary conditions and to perform according to a specified standard. Typical conditions include, for example, performance over operating temperature ranges, sensitivity to noise, output sensitivity to interference, and the like. Typical performance standards include, for example, Input signal jitter tolerance, output signal frequency stability, output signal programmability, and the like.
A typical prior art CDR circuit generates an oscillating output clock signal having a specified frequency, and recovered data. The frequency of the output is tunable and is a function of an input data, or the like. The type of application in which the CDR circuit is used dictates its operating conditions and performance requirements.
In addition, the type of application also largely determines type of fabrication technology used to manufacture the CDR. A large number of modern digital integrated circuits are fabricated using well known and widely used CMOS technology. Where the CDR circuit is included in a CMOS IC (integrated circuit), it is usually fabricated in CMOS (e.g., fabricated using CMOS process technology).
There is a problem, however, when the application in which the overall IC is used requires the CDR circuit to handle input data with long CID. For example, where the IC is part of a high speed serial transmission system (e.g., high speed optical communication systems) it is important that the CDR to have good jitter tolerance when CID is long. Prior art CMOS CDRs have tried to solve this issue. Typically digital CDRs are used to handle long CIDs. However, because of the fact that in digital CDRs the loop is very slow, it will be problematic for some applications, and make the system unreliable.
Thus, what is required is a CMOS CDR circuit which solves the problems of the prior art. What is required is a circuit capable of reliable operation while exhibiting good jitter tolerance when CID is long. What is required is a circuit with high jitter tolerance free of defects and irregularities even when the input pattern has long CID. The present invention provides an advantageous solution to the above requirements.